1. Field of the Invention
The present invention relates to a video signal processing apparatus such as a resolution processing apparatus or the like for artificially enhancing the resolution of video data.
2. Description of Related Art
Currently, multi-scan display devices are predominant in display devices for use with personal computers, as they can support a variety of display modes which may have the resolution of 640 (horizontal direction)xc3x97480 (vertical direction) dots; 800xc3x97600 dots; 1024xc3x97768 dots; or 1600xc3x971200 dots. For displaying video data having the resolution of 800xc3x97600 dots on a full screen of such a display device when it is in a mode of displaying, for example, 1600xc3x971200 dots, signal processing is performed to scale up the video data by a factor of two both in the vertical direction and in the horizontal direction to enhance the resolution of the video data to 1600xc3x971200 dots.
A video signal in accordance with a television standard such as the NTSC standard, has a predefined resolution. Therefore, a television receiver for treating video signals of such the television standard supports the resolution corresponding to this video signal. In recent years, however, high definition television receivers have become commercially available for displaying a video image in a higher resolution than that defined in the television standard. Specifically, the high definition television receiver enlarges a video signal in each of the vertical direction and the horizontal direction, by a desired factor in each direction, to artificially enhance the resolution of a video image, thereby allowing the video image displayed in such a higher resolution.
In this way, such high definition television receivers and the aforementioned personal computers have implemented a resolution change for enlarging an incoming video signal (video data) by a factor of n in each of the vertical direction and the horizontal direction to artificially enhance the resolution of the video signal.
FIG. 1 illustrates a resolution processing apparatus for performing the resolution change, as mentioned above, for incoming video data.
Referring specifically to FIG. 1, the resolution processing apparatus comprises a sampling frequency conversion unit 1; a horizontal resolution processing circuit 5; a vertical resolution processing circuit 6; and a resolution processing control circuit 15.
A timing detector circuit 3 in the sampling frequency conversion unit 1 detects a sampling timing of an incoming video data sequence D composed, for example, of series of 8-bit video data, and supplies a line memory 2 with a write signal in response to each detected timing. It should be noted that each of the video data corresponds to each pixel on a display device 14, later described. The line memory 2 sequentially fetches each video data in the video data sequence D in response to the write signal. The video data sequence D fetched in the line memory 2 as mentioned above is read therefrom in the fetched order in response to a read signal supplied to the line memory 2 from the resolution processing control circuit 15, later described, and supplied to the horizontal resolution processing circuit 5 as a video data sequence DC. The line memory 2 is organized, for example, of FIFO (First In First Out) memories or the like which have a storage capacity for one horizontal scanning line (hereinafter called the xe2x80x9c1Hxe2x80x9d) in the video data, and which can simultaneously and independently execute a write operation and a read operation.
With the configuration as mentioned, the sampling frequency conversion unit 1 converts the sampling frequency of the incoming video data sequence D to a higher sampling frequency which is adapted to the processing rate of the resolution processing apparatus (for the video data sequence DC), and supplies the higher sampling frequency to the horizontal resolution processing circuit 5.
The sampling frequency is converted for the following reason.
For displaying a moving image, an incoming video signal must be displayed without interruption. However, when the video signal is subjected to a variety of resolution enhancement processing, a continuous display of the moving image cannot be maintained occasionally due to the influence of a delay caused by the processing. To solve this problem, the sampling frequency conversion unit 1 is used to increase the sampling frequency of the incoming video data sequence D (corresponding to the video signal) to provide a higher processing rate in the resolution enhancement processing.
The horizontal resolution processing circuit 5 interpolates the video data sequence DC having the sampling frequency increased by the sampling frequency conversion unit 1 to generate a video data sequence DCH with an enhanced resolution in the horizontal direction, and supplies the vertical resolution processing circuit 6 with the video data sequence DCH.
A line memory 7 in the vertical resolution processing circuit 6 delays the video data sequence DCH by a time corresponding to 1H of the video data sequence DCH to generate a delayed video data sequence DDCH which is output therefrom. In this event, the line memory 7 is organized, for example, of FIFO (First In First Out) memories or the like which have a storage capacity for 1H video data in the video data sequence DCH.
A mixer circuit 9 is composed of a first multiplier for multiplying the current video data sequence DCH by a coefficient K1; a second multiplier for multiplying a 1H delayed video data sequence DDCH by a coefficient (1xe2x88x92K1); and a first adder for adding outputs of the first and second multipliers to generate one line portion of first interpolated image data. Then, the mixer circuit 9 generates a 1H portion of a first video data sequence DHVI by the following calculation (1) using the foregoing video data sequence DCH, delayed video data sequence DDCH, and predetermined coefficient K1, and supplies the first video data sequence DHVI to a frame memory 11:
DHVI=DDCHxc2x7K1+DDCH(1xe2x88x92K1)xe2x80x83xe2x80x83(1)
A mixer circuit 10, which has a similar configuration to that of the mixer circuit 9, generates a 1H portion of a second video data sequence DHV2 by the following calculation (2) using the foregoing video data sequence DCH and delayed video data sequence DDCH, and a predetermined coefficient K2, and supplies the second video data sequence DHV2 to the frame memory 11:
DHV2=DCHxc2x7K2+DDCH(1xe2x88x92K2)xe2x80x83xe2x80x83(2)
The predetermined coefficients K1, K2 have coefficient values in accordance with the degree to which the resolution is enhanced, and are generated by the resolution processing control circuit 15.
With the configuration as described, the vertical resolution processing circuit 6 newly generates 2H portions of video data sequences (DHHV1, DHV2) based on a 1H portion of video data sequence in the video data sequence DCH, and a video data sequence 1H before this video data sequence. Thus, a video data sequence having the number of horizontal scanning lines twice as much as the incoming original video data sequence D is generated, thereby enhancing the vertical resolution. It should be noted that each of the predetermined coefficients K1, K2 has a coefficient value in accordance with the degree to which the resolution is enhanced, and is generated by the resolution processing control circuit 15.
The frame memory 11 alternately stores the first video data sequence DHV1 and the second video data sequence DHV2. Subsequently, the stored image data are sequentially read from the frame memory 11, and supplied to the display device 14 of a matrix display type such as a plasma display panel, by way of example, as a high definition video data sequence DH. One screen of the display device 14 may be formed of (nxc2x7m) pixels in a matrix of n rows and m columns. In this configuration, the number of rows n indicates the vertical resolution, while the number of columns m indicates the horizontal resolution. They correspond to the resolution in the high definition video data sequence DH.
As described above, in the resolution processing apparatus illustrated in FIG. 1, an incoming video data sequence is interpolated to enhance the horizontal resolution. Further, 2H portions of video data are generated from a 1H portion of video data in such a video data sequence to enhance the vertical resolution by a factor of two.
In the configuration illustrated in FIG. 1, however, since the horizontal resolution processing circuit 5 causes an increase in the amount of data corresponding to 1H due to an enhanced horizontal resolution in the video data, the storage capacity of the line memory 7 must be increased due to the increase in the amount of data.
For example, the line memory 7 requires a storage capacity for 2H portions of video data when the horizontal resolution processing circuit 5 enhances the horizontal resolution by a factor of two; 3H portions of video data when enhancing by a factor of three; and 4H portions of video data when enhancing by a factor of four.
As will be appreciated, the configuration illustrated in FIG. 1 implies a problem in that the scale of the apparatus is increased in proportion to the degree of the resolution enhancement.
In addition, without limited to the foregoing configuration, three or more mixers and data lines can be provided for one input. For example, when three each of mixers and data lines are provided for one input, three outputs can be generated for one input, so that a resulting image can be enlarged maximally by a factor of three in the vertical direction.
For example, for enlarging a video signal having pixels in a matrix form of horizontally 640xc3x97vertically 480 by a factor of three both in the horizontal and vertical directions, the foregoing configuration requires a line memory having the capacity of 640 pixels as the line memory 2 and a line memory having the capacity of 1,920 pixels as the line memory 7, because the vertical enlargement processing is performed after the horizontal enlargement processing, thus requiring the total capacity of 2,560 pixels.
In this case, the resolution processing circuit would require the number of data lines equal to the scaling factor, i.e., three data lines, and a total of six multipliers in the mixer circuits.
As described above, the conventional circuit configuration must be provided with a complicated mixer circuit sufficient for accommodating a scaling factor in the vertical direction, and a corresponding number of data lines. This leads to another problem that the circuit configuration must be modified each time the scaling factor is changed in the vertical direction.
The present invention has been made to solve the problems mentioned above, and is intended to provide an apparatus for enhancing the resolution of video data in a smaller apparatus scale.
It is another object of the present invention to provide a video signal processing apparatus which is capable of changing an scaling factor without modifying its circuit configuration.
According to a first feature, the present invention provides an apparatus for enhancing the resolution of video data adapted to enhance the resolution of an incoming video data sequence composed of a plurality of video data each corresponding to a pixel, to generate a high definition video data sequence, the apparatus comprising vertical resolution enhancement processing means including a plurality of memories for sequentially storing one horizontal scanning line portion of each video data in the incoming video data sequence, reading means for repetitively reading a first video data group having the one horizontal scanning line portion of video data and a second video data group having video data one horizontal scan period before the first video data group from the memories N times (where N is a natural number) within the one horizontal scan period, and mixing means for mixing the first video data group and the second video data group with a mixing ratio, where the mixing ratio is switched each time the video data groups are read from the memories, to generate a video data sequence having the resolution enhanced in the vertical direction by a factor of N; and horizontal resolution enhancement processing means for interpolating the video data sequence to generate a video data sequence having the resolution enhanced in the horizontal direction, and for outputting the video data sequence as the high definition video data sequence.
According to a second feature, the present invention provides a video signal processing apparatus comprising first and second line memories each for storing one horizontal scanning line portion of video data sequence; control means for alternately writing every horizontal scanning line of an incoming video data sequence into the line memories, and for controlling the line memories to read video data sequences therefrom; and processing means for mixing a first video data sequence read from the first line memory and a second video data sequence read from the second line memory using a coefficient to create one horizontal scanning line portion of a new video data sequence, wherein the control means repetitively reads video data sequences from the line memories a plurality of times within a time length corresponding to one horizontal scanning line portion when the video data sequence has been input, and the control means further changes the coefficient each time video data sequences are read.
According to the video signal processing apparatus of the present invention, video data sequences are repetitively read from the respective line memories a plurality of times within a time length corresponding to a 1H portion of an incoming video data sequence, and different coefficients for use in mixing the two video data sequences from the line memories are switched each time the video data sequences are read, so that a plurality of new video data sequences can be created from a current video data sequence in a time division manner in a single mixer circuit.